This application claims priority from Korean Patent Application No. 2001-28257, filed May 23, 2001, the contents of which are herein incorporated by reference in their entirety.
1. Field of the Invention
The present invention relates to an electrically erasable and programmable nonvolatile semiconductor memory device, and more particularly to an improved sector structure of a nonvolatile semiconductor memory device.
2. Description of Related Art
Semiconductor memory devices are generally classified as either volatile or nonvolatile devices. Volatile semiconductor memory devices are further classified as either dynamic random access memory (DRAM) devices or static random access memory (SRAM) devices. Volatile memory devices perform quick read and write operations, but unfortunately lose the contents stored in their memory cells when an external power supply is cut off.
Nonvolatile semiconductor memory devices are further classified as mask read only memory (MROM) devices, programmable read only memory (PROM) devices, or electrically erasable and programmable read only memory (EEPROM) devices. A nonvolatile memory device is able to permanently store the contents of its memory cells even when an external power supply is cut off. Nonvolatile memory devices are therefore preferred for storing information that must be retained despite power loss.
In MROM and PROM devices, however, it is inconvenient to erase or re-program the contents programmed therein at the on-board state. Common users are therefore unable to perform the erase and write (or program) processes. In EEPROM devices, on the other hand, the electrical erase and write processes are conveniently available. For these reasons, EEPROM devices have continuously grown in popularity for use in applications requiring a system program storage device or an auxiliary memory device where the continuous renewal of its contents is desirable.
NOR-type flash EEPROMs, in particular, which provide a flash erase function, have been welcomed by users who demand a high speed memory device offering faster programming, write, and read operations than NAND-type or AND-type EEPROMs. The general operation of a conventional NOR-type flash memory device will be described below to provide a more thorough understanding of the present invention.
FIG. 7 is a cross-sectional view of a memory cell transistor forming a memory cell unit of a conventional NOR-type flash memory device. Referring to FIG. 7, an n-type source region 3 is formed on a p-type substrate 2, and an n-type drain region 4 is formed with a p-type channel region apart from the source region 3. A floating gate electrode 6, insulated by a thin insulating layer 7 having a thickness less than 100 angstroms, is formed on the p-type channel region. A control gate 8 (which may be called a word line) is formed over another insulating layer 7 above the floating gate electrode 6.
Referring to FIG. 8, the operation of the memory cell transistor of FIG. 7 will now be described. FIG. 8 is a table indicating voltage levels to be applied to the transistor depending on the operational mode of the semiconductor device. The semiconductor device operational modes include a program mode, an erase mode, and a read mode. Although not shown in FIG. 8, an erase repair mode is also provided.
The program operation is performed by injecting hot electrons from the drain region 4 and its adjacent channel region 5 into the floating gate electrode 6. As shown in FIG. 8, the hot electrons for the program operation are generated by applying a high level of voltage (e.g., 10V) to the control gate electrode 8 and by applying an adequate level of voltage (e.g., 5-6V) to the drain region 4. The source region 3 and the p-type substrate region 2 are grounded. Hot electrons are thereby injected into the floating gate electrode 6. After negative charges have been sufficiently accumulated at the floating gate electrode 6, the memory cell transistor has a higher level of threshold voltage than it had prior to the program operation. More specifically, a programmed memory cell transistor generally has voltage distribution in the range of 6 to 7V. A programmed memory cell transistor is called xe2x80x9can off-cell.xe2x80x9d
The read operation is performed by applying a positive voltage level (e.g., 1V) to the drain region 4 and a predetermined voltage level (e.g., 4.5V) to the control gate electrode 8. The source region 3 and the substrate region 2 are grounded. As noted above, after the program operation, a programmed memory cell transistor has a higher threshold voltage and therefore functions as an off-cell during the read operation. A programmed cell operates as an off-cell because it prevents current flow from the drain region 4 to the source region 3 during the read operation.
In the NOR-type flash memory cell transistor, the erase operation is performed by generating a Fowler-Nordheim tunneling phenomenon (F-N tunneling) between a bulk region formed in the substrate 2 and the control gate electrode 8. F-N tunneling requires a high level of negative voltage (e.g., xe2x88x9210V) to be applied to the control gate electrode 8 and an adequate level of positive voltage (e.g., 5V) to be applied to the bulk region 2. The drain region 4 is set at high impedance to ensure an effective erase operation.
These erase operation conditions create a strong magnetic field between the control gate electrode 8 and the bulk region, causing F-N tunneling. The negative charges at the floating gate electrode 6 are thereby discharged to the source region 3. The F-N tunneling occurs when a magnetic field of between 6 to 7 MV/cm is applied to the conductive layer 6 between the insulating layers 7. In the aforementioned memory cell transistor, each gate insulating layer 7 is formed having a thickness of about 100 angstroms to facilitate the F-N tunneling. As a result of the erase operation, the level of threshold voltage at the memory cell transistor ranges between approximately 1V to 3V. The threshold voltage is therefore lower than following the program operation, when electric charges are accumulated at the floating gate electrode 6, and an erased memory cell transistor is called an xe2x80x9con-cellxe2x80x9d.
In the conventional flash memory device, a plurality of cells are connected to a common bulk region to provide a high memory integration density. In this manner, all of the memory cells in the common bulk region can be simultaneously erased during the erase operation. Erase units, or sectors, are formed as divided regions of the flash memory. An erase region can, for instance, comprise a 64 Kbyte sector.
During the read operation, a memory cell having a threshold voltage level lowered during the erase operation functions as an on-cell because a current path is formed from a drain region to a source region. Unfortunately, an erase operation performed to lower the threshold voltage of the memory cell transistors may result in threshold voltages lower than 0V, beyond the erased voltage cell range of 1V to 3V. This over-erasing results from non-uniformity between threshold voltages of the various memory cell transistors. Memory cell transistors having threshold voltages less than 0V are called xe2x80x9cover-erased cells.xe2x80x9d Over-erased memory cells require a curing operation (or erase-repair operation) to increase the threshold voltages to within the erased voltage range of between about 1V to 3V.
The erase-repair operation can be performed by grounding the source region 3 of the over-erased memory cell transistors and the p-type substrate 2, and applying a positive voltage level (e.g., 2V to 5V) to the control gate electrode 8. Another positive voltage level (e.g., 6V to 9V) is applied to the drain region 4. As a result of the erase-repair operation, an amount of negative charge, less than that of the program operation, is accumulated at the floating gate electrode 6 to cause it to remain at the threshold voltage range of about 1V to 3V.
In order to apply appropriate voltages to the memory cell transistors to perform the programming, reading, and erasing operations, each sector of the conventional NOR-type semiconductor device has a structure similar to that shown in FIG. 1. Referring now to FIG. 1, each sector has a cell array block 101 including a plurality of memory cell transistors M1-Mnm that form a memory cell array. The cell array block 101 includes a plurality of word lines WL0 to WLn-1 . Each of the word lines WLi is commonly connected to n number of cell gates. In addition, a plurality of bit lines BL0 to BLm-1 are formed therein, wherein each of the bit lines BLi is commonly connected to m cell drains.
A column decoder block 102 is connected to the cell array block 101 to perform a decoding operation. The m number of bit lines are connected to each of the common data lines DLi through a corresponding column decoder. The common data lines include I number of lines DL0 to DLI-1. The common data lines are respectively connected to corresponding write drivers 200, 201 and sense amplifiers 300, 310. All of the source terminals of the memory cell transistors in the cell array block 101 are connected to a common source line SL, driven by the source line driver 500. All of the memory cell transistors are further connected to a common bulk line Bulk at its bulk terminals. The common bulk line Bulk is driven by the bulk driver 400. The transistors T1, T2, T3 in the column decoder block 102 are formed in a separate bulk, which is grounded to 0V.
Referring to FIG. 2, the bulk region 10 of the cell array block 101 and the bulk region 11 of the column decoder block 102 are separately and independently formed in a common substrate 1, so that a high voltage does not affect the data lines during an erasing operation. For example, when a high voltage (e.g., 5V) is applied to the bulk terminal (Bulk) of the cell array block 101 while an erasing operation is performed using a channel erase scheme, the high voltage is prevented from being applied to the data line DL. More specifically, the pass signal YPASSi (e.g., 0V) is applied to the gates of the transistors in the column decoder block 102 so that the data line DL will not be influenced by the high voltage.
Unfortunately, however, because the P-well bulk region 10 of the cell array block 101 must be spaced a predetermined distance apart from the P-well bulk region 11 of the column decoder block 102, the separately formed bulks of the conventional device result in an increase in the layout area of a chip and hence chip size. This increase in size limits the degree of integration available in the semiconductor device. In addition, the greater the number of cell array blocks 101 and column decoder blocks 102, the larger the required chip size and the greater the impediment to a high degree of integration.
Because the bulks of the transistor devices in the cell array block and column decoder block of the conventional NOR-type flash memories are separately and independently formed, a lower integration density is available. The industry is in need of an EEPROM for use in a variety of computer or microprocessor controlled electronic devices that can be electrically erasable or programmable at a high speed and which occupies a minimal layout area. It is also desirable to replace conventional hard disk devices with EEPROM memory devices having minimal layout areas. Conventional hard disk devices used as auxiliary memory devices in battery powered computer systems include a rotary magnetic disk and occupy a relatively large area. Designers of portable computers and notebook computers have therefore been interested in the development of an EEPROM having a compact size and high speed operation that can replace these hard disk devices.
An object of the present invention is to provide a method of sharing bulk regions to minimize or reduce a layout area in a NOR-type nonvolatile semiconductor device.
Another object of the present invention is to provide a method of forming a bulk region of a column decoder in a NOR-type nonvolatile semiconductor device.
Still another object of the present invention is to provide a bulk region structure of a cell array block and a column decoder block in a nonvolatile semiconductor memory device.
Yet another object of the present invention is to reduce chip area by providing a nonvolatile semiconductor memory device with a sector structure having a common bulk region.
In accordance with one aspect of the present invention, a sector structure of a nonvolatile semiconductor memory device includes memory cell transistors in a cell array block and transistors in a column decoder block. The cell array block and column decoder block share a common bulk region.
In accordance with another aspect of the present invention, a method of forming a bulk region of a column decoder in a NOR-type nonvolatile semiconductor device includes providing a common bulk region for transistors in a column decoder block and memory cell transistors in a cell array block.